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STP40N03L-20
N - CHANNEL ENHANCEMENT MODE "ULTRA HIGH DENSITY" POWER MOS TRANSISTOR
PRELIMINARY DATA TYPE ST P40N03L-20
s s s s s s s
V DSS 30 V
R DS(on) < 0.02
ID 40 A
TYPICAL RDS(on) = 0.016 AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE HIGH dV/dt CAPABILITY APPLICATION ORIENTED CHARACTERIZATION TO-220
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2
3
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s POWER MOTOR CONTROL s DC-DC & DC-AC CONVERTERS s SYNCRONOUS RECTIFICATION
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM (*) P to t Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating Factor dV/dt(1) T st g Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature
o o o
Value 30 30 15 40 28 160 90 0.6 6 -65 to 175 175
Unit V V V A A A W W/ C V/ns
o o o
C C
(*) Pulse width limited by safe operating area
March 1996
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STP40N03L-20
THERMAL DATA
R t hj-ca se R t hj- amb R thc- si nk Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead T emperature For Soldering Purpose Max Max Typ 1.66 62.5 0.5 300
o o
C/W C/W o C/W o C
AVALANCHE CHARACTERISTICS
Symb ol I AR E AS E AR I AR Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy o (starting Tj = 25 C, ID = I AR , V DD = 25 V) Repetitive Avalanche Energy (pulse width limited by Tj max, < 1%) Avalanche Current, Repetitive or Not-Repetitive o (T c = 100 C, pulse width limited by Tj max, < 1%) Max Valu e 40 300 75 28 Unit A mJ mJ A
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 A VGS = 0 Min. 30 250 1000 100 Typ . Max. Un it V A A nA
Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating x 0.8 T c = 125 o C Gate-body Leakage Current (V DS = 0) V GS = 15 V
ON ()
Symb ol V GS(th) R DS( on) Parameter Gate T hreshold Voltage V DS = VGS Static Drain-source On Resistance On State Drain Current Test Cond ition s ID = 250 A T c = 100 o C 0.019 40 Min. 1 Typ . 1.6 0.016 Max. 2 0.02 0.04 0.023 Un it V A
V GS = 10V I D = 20 A V GS = 10V ID = 20 A V GS = 5V I D = 20 A V DS > I D(on) x R DS(on) max V GS = 10 V
ID(o n)
DYNAMIC
Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Cond ition s V DS > I D(on) x R DS(on) max V DS = 25 V f = 1 MHz I D = 20 A VGS = 0 Min. 15 Typ . 22 1800 450 180 2300 580 230 Max. Un it S pF pF pF
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STP40N03L-20
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symb ol t d(on) tr (di/dt) on Parameter Turn-on T ime Rise Time Turn-on Current Slope Test Cond ition s V DD = 15 V ID = 10 A VGS = 5 V R G = 4.7 (see test circuit, figure 3) V DD = 24 V ID = 20 A R G = 50 V GS = 5 V (see test circuit, figure 5) V DD = 24 V ID = 20 A V GS = 5 V Min. Typ . 20 80 200 Max. 30 100 Un it ns ns A/s
Qg Q gs Q gd
Total Gate Charge Gate-Source Charge Gate-Drain Charge
40 10 20
60
nC nC nC
SWITCHING OFF
Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over T ime Test Cond ition s V DD = 24 V I D = 20 A R G = 4.7 V GS = 5 V (see test circuit, figure 5) Min. Typ . 42 45 76 Max. 55 60 100 Un it ns ns ns
SOURCE DRAIN DIODE
Symb ol I SD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 40 A V GS = 0 65 0.12 4 I SD = 20 A di/dt = 100 A/s o Tj = 150 C V DD = 24 V (see test circuit, figure 5) Test Cond ition s Min. Typ . Max. 40 160 1.5 Un it A A V ns C A
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area (1) ISD 40 A, di/dt 300 A/s, VDD V(BR)DSS, Tj TJMAX
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STP40N03L-20
PSPICE PARAMETERS SUBCIRCUIT COMPONENTS
Symb ol S1 S2 LD LG LS RDRAIN RG ATE CG D CGS ALFA RG N Parameter (V14_16<0) (See Power Mosfet Model Subcircuit) (V16_11<0) (See Power Mosfet Model Subcircuit) Drain Inductance Gate Inductance Source Inductance Drain Resistance Gate Resistance Gate Drain Capacitance Gate Source Capacitance Drift Coeficient Negative Bias Resistance Valu e ON ON 8 10 10 1.9E 1 3.92 1.9 1E
-3 -2
Unit
nH nH nH nF nF V -1 K
10
DIODE DRAIN GATE (Depletion Capacitance)
Symb ol CJO VJ M Parameter Zero Bias p-n Capacitance p-n Potential p-n G rading Coefficient Valu e 2.7 0.35 0.55 Unit nF V
DIODE DRAIN SOURCE
Symb ol CJO VJ M TT Parameter Zero Bias p-n Capacitance p-n Potential p-n G rading Coefficient Transit Time Valu e 10 0.35 0.55 20 nsec Unit nF V
N MOSFET
Symb ol L W LEVEL TO X VT O U0 THETA Vmax KP Channel Length Channel Width Model Index Oxide Thickness Zero Bias Threshold Voltage Surface Mobility Mobility Modulation Maximum Drift Velocity Trans Conductance Coefficient Parameter Valu e 1 1 3 1 3.25 600 0.005 0 15 Meter V cm /VS V -1 Meter/sec Amp/V
2 2
Unit Meter Meter
For Transient Simulation Applicate U.I.C. (Use Initial Condition) Option
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STP40N03L-20
PSPICE NETLIST OF THE SUBCIRCUIT
.SUBCKT STP40N03L-20 1 2 3 *VALUE OF THE PACKAG E INDUCTANCES LS 1 11 10n LG 2 12 10n LD 3 13 7n *RESISTA NCE O F T HE G AT E POLYSILICON RG 12 16 1 *EPY AND DRIF T RESISTANCES RD 13 14 1.9e-02 EDRI 14 15 POLY(2) (13 14) (13 11) 0 0 0 0 1e-3 *CAPACITANCE G ATE SO URCE CGS 16 11 1.90n *OPT IO NAL FO R NEGAT IVE GATE BIAS *S2 51 11 11 16 SWITCH *CGN 51 16 3.92n *RGN 51 16 10k *MILLER CAPACITANCE CGD 16 17 3.92n * DEPLET ION CAPACIT ANCE DGD 17 14 DGD S1 17 14 16 14 SW ITCH .MODEL DGD D +IS= +CJO =2.6n +Vj=.1 +M=.6 .MODEL SWITCH VSW IT CH +RON=1m +ROF F=1MEG +VON=0.1 * OUTPUT CAPACITANCE AND BODY DRAIN DIODE DBD 11 14 DBD .MODEL DBD D +TT=20n +CJO =7.8n +VJ=.1 +M=.6 * MO DEL OF THE MO SF ET MMAI N 15 16 11 11 MMAIN L=1u W =1u .MODEL MMAIN NMO S +LEVEL=3 +TOX=1 +VTO =3.25 +uo=600 +THETA=0.005 +VMAX=5e7 +KP=28 .ENDS
Power Mosfet Model Subcircuit
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STP40N03L-20
TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147
E
mm TYP. MAX. 4.60 1.32 2.72 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 MIN. 0.173 0.048 0.094 4.40 1.23 2.40
inch TYP. MAX. 0.181 0.051 0.107 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 0.645 0.551 0.116 0.620 0.260 0.154 0.151
A
C
D1
L2 F1
D
G1
Dia. F2 F
L5 L7 L6
L9
L4
G
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H2
P011C
STP40N03L-20
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersede and replaces all information previously supplied. s SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ...
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